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? 1999 microchip technology inc. preliminary ds30026a-page 1 pic16lc74b-16/ptl16 microcontroller core features: ? high-performance risc cpu ? specially tested -16mhz @ 3v ? only 35 single word instructions to learn ? all single cycle instructions except for program branches which are two cycle ? operating speed: dc - 16 mhz clock input dc - 250 ns instruction cycle ? 4k x 14 words of program memory, 192 x 8 bytes of data memory (ram) ? interrupt capability ? eight level deep hardware stack ? direct, indirect and relative addressing modes ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code-protection ? power saving sleep mode ? selectable oscillator options ? low-power, high-speed cmos eprom technology ? wide operating voltage range: 2.5v to 5.5v ? high sink/source current 25/25 ma ? commercial, industrial and automotive temperature ranges ? low-power consumption: - < 5 ma @ 5v, 4 mhz - 23 m a typical @ 3v, 32 khz -< 3 m a typical standby current pin diagram: peripheral features: ? timer0: 8-bit timer/counter with 8-bit prescaler ? timer1: 16-bit timer/counter with prescaler can be incremented during sleep via external crystal/clock ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? capture, compare, pwm module(s) - capture is 16 bit, max. resolution is 15.6 ns - compare is 16 bit, max. resolution is 250 ns - pwm max. resolution is 10 bit ? 8-bit multichannel analog-to-digital converter ? synchronous serial port (ssp) with spi ? and i 2 c ? ? universal synchronous asynchronous receiver transmitter (usart/sci) ? parallel slave port (psp), 8-bits wide, with external rd , wr and cs controls ? brown-out detection circuitry for brown-out reset (bor) pin diagrams nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/cs/an7 re1/wr/an6 re0/rd/an5 ra5/ss/an4 ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 tqfp pic16lc74b-16/ptl16 pic16lc74b-16/ptl16 8-bit cmos microcontrollers with a/d converter
pic16lc74b-16/ptl16 ds30026a-page 2 preliminary ? 1999 microchip technology inc. table of contents 1.0 general description ......................................................................................................... ........................................ 3 2.0 electrical characteristics.................................................................................................. ........................................ 5 3.0 dc and ac characteristics graphs and tables................................................................................. .................... 27 4.0 packaging information ....................................................................................................... .................................... 29 index .......................................................................................................................... ................................................... 33 on-line support ................................................................................................................ ............................................ 35 reader response ................................................................................................................ ......................................... 36 product identification system.................................................................................................. ...................................... 37 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. the last character of the literature number is the version number. e.g., ds30000a is version a of doc- ument ds30000. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and rec- ommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchips worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literature center; u.s. fax: (602) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. corrections to this data sheet we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that this document is correct. however, we realize that we may have missed a few things. if you find any information that is missing or appears in error, please: ? fill out and mail in the reader response form in the back of this data sheet. ? e-mail us at webmaster@microchip.com. we appreciate your assistance in making this a better document.
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 3 1.0 general description this data sheet covers the pic16lc74b-16/ptl16 device. the functional characteristics of this device are identical to the pic16lc74b. for electrical specifica- tions, see the electrical specifications contained within this document. for all other information about this device, see the pic16c63a/65b/73b/74b data sheet (ds30605).
pic16lc74b-16/ptl16 ds30026a-page 4 preliminary ? 1999 microchip technology inc. notes:
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 5 2.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ........... .-55c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr , and ra4).......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2).......................................................................................... 0v to +13.25v voltage on ra4 with respect to vss ............................................................................................. .................. 0v to +8.5v total power dissipation (note 1)............................................................................................... .................................1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta, portb, and porte (combined)..................................................................200 ma maximum current sourced by porta, portb, and porte (combined) ............................................................200 ma maximum current sunk by portc and portd (combined) ................................................................................200 ma maximum current sourced by portc and portd (combined) ...........................................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a low level to the mclr /v pp pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device, at those or any other conditions above those indicated in the operation listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16lc74b-16/ptl16 ds30026a-page 6 preliminary ? 1999 microchip technology inc. figure 2-1: pic16lc74b-16/ptl16 voltage-frequency graph frequency (mhz) voltage (v dd ) 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 16 mhz 5.0 v 3.5 v 3.0 v 2.5 v 4 mhz 8 mhz fmax = (24 mhz/v)(v dd . app . min - 2.5v) + 4 mhz note: v dd . app . min is the minimum v dd of the picmicro ? device in the application. fmax is no greater than 16 mhz.
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 7 2.1 dc characteristics: pic16lc74b-16/ptl-04 (commercial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial param no. sym characteristic min typ? max units conditions d001 v dd supply voltage 2.5 v bor * - - 5.5 5.5 v v rc, lp, xt, hs osc modes (dc - 4 mhz) bor enabled (note 7) d002* v dr ram data retention voltag e (note 1) -tbd- v d003 v por v dd start voltage to ensure internal power-on reset signal -v ss -v d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 tbd - - - - v/ms v/ms pwrt enabled (pwrte bit clear) pwrt disabled (pwrte bit set) d005 v bor brown-out reset voltage trip point 3.65 - 4.35 v boden bit set d010 d010a i dd supply current (note 2, 5) - - - 2.0 3.0 22.5 3.8 6.0 48 ma ma m a xt, rc osc modes f osc = 4 mhz, v dd = 3.0v (note 4) hs oscillator mode fosc = 16mhz, v dd = 3.0v lp osc mode f osc = 32 khz, v dd = 3.0v, wdt disabled d021 i pd power-down current (note 3, 5) -0.95 m av dd = 3.0v, wdt disabled, 0 c to +70 c d022* d022a* d i wdt d i bor module differential current (note 6) watchdog timer brown-out reset - - 6.0 350 20 425 m a m a wdte bit set, v dd = 4.0v boden bit set, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd . mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through rext is not included. the current through the resistor can be estimated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the specification. this value is from charac- terization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
pic16lc74b-16/ptl16 ds30026a-page 8 preliminary ? 1999 microchip technology inc. 2.2 dc characteristics: pic16lc74b -16/ptl-04 ( commercial ) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 2.1 param no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 d030a with ttl buffer v ss v ss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss -0.2v dd v d032 mclr , osc1 (in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp modes) vss - 0.3v dd vnote1 input high voltage v ih i/o ports - d040 with ttl buffer 2.0 - v dd v4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp modes) 0.7v dd -v dd vnote1 d043 osc1 (in rc mode) 0.9v dd -v dd v input leakage current (notes 2, 3) d060 i il i/o ports - - 1 m avss v pin v dd , pin at hi-impedance d061 mclr , ra4/t0cki - - 5 m avss v pin v dd d063 osc1 - - 5 m avss v pin v dd , xt, hs and lp osc modes d070 i purb portb weak pull-up current 50 250 400 m av dd = 5v, v pin = v ss output low voltage d080 v ol i/o ports - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c --0.6vi ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc mode) --0.6vi ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c --0.6vi ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c output high voltage d090 v oh i/o ports (note 3) v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c * these parameters are characterized but not tested. ? data in typ column is at 3v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the device be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 9 v dd -0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc mode) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c v dd -0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150* v od open-drain high voltage - - 8.5 v ra4 pin capacitive loading specs on output pins d100 c osc2 osc2 pin - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 c io all i/o pins and osc2 (in rc mode) --50pf d102 cb scl, sda in i 2 c mode - - 400 pf 2.2 dc characteristics: pic16lc74b -16/ptl-04 ( commercial ) (c ont.d) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 2.1 param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in typ column is at 3v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the device be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic16lc74b-16/ptl16 ds30026a-page 10 preliminary ? 1999 microchip technology inc. 2.3 ac (timing) characteristics 2.3.1 timing parameter symbology the timing parameter symbols have been created using one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t ffrequency ttime lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 11 2.3.2 timing conditions the temperature and voltages specified in table 2-1 apply to all timing specifications unless otherwise noted. figure 2-2 specifies the load conditions for the timing specifications. table 2-1: temperature and voltage specifications - ac figure 2-2: load conditions for device timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 2.1. lc parts operate for commercial/industrial temps only. v dd /2 c l r l pin pin v ss v ss c l r l =464 w c l = 50 pf for all pins except osc2/clkout but including d and e outputs as ports 15 pf for osc2 output load condition 1 load condition 2
pic16lc74b-16/ptl16 ds30026a-page 12 preliminary ? 1999 microchip technology inc. 2.3.3 timing diagrams and specifications figure 2-3: external clock timing table 2-2: external clock timing requirements param no. sym characteristic min (note 2) typ? max (note 3) units conditions 1a fosc external clkin frequency (note 1) dc 4 mhz rc and xt osc modes dc 4 mhz hs osc mode (-04) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1tosc external clkin period (note 3) 250 ns rc and xt osc modes 250 ns hs osc mode (-04) 50 ns hs osc mode (-20) 5 m slp osc mode oscillator period (note 3) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 50 250 ns hs osc mode (-20) 5 m slp osc mode 2t cy instruction cycle time (note 1) 200 dc ns t cy = 4/fosc 3* tosl, to s h external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4* tosr, to s f external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. 2: all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. 3: when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 13 figure 2-4: clkout and i/o timing table 2-3: clkout and i/o timing requirements param no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - tosc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18a* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20a* tior port output rise time 80 ns 21a* tiof port output fall time 80 ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 2.1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16lc74b-16/ptl16 ds30026a-page 14 preliminary ? 1999 microchip technology inc. figure 2-5: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 2-6: brown-out reset timing table 2-4: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m s v dd = 5v, -40c to +125c 31* twdt watchdog timer time-out period (no prescaler) 71833ms v dd = 5v, -40c to +125c 32 tost oscillation start-up timer period 1024 t osc t osc = osc1 period 33* tpwrt power-up timer period 28 72 132 ms v dd = 5v, -40c to +125c 34 t ioz i/o hi-impedance from mclr low or wdt reset 2.1 m s 35 t bor brown-out reset pulse width 100 m s v dd bv dd (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 2-2 for load conditions. v dd bv dd 35
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 15 figure 2-7: timer0 and timer1 external clock timings table 2-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4,..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 25 ns asynchronous 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 25 ns asynchronous 50 ns 47* tt1p t1cki input period synchronous greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc 200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 2-2 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1
pic16lc74b-16/ptl16 ds30026a-page 16 preliminary ? 1999 microchip technology inc. figure 2-8: capture/compare/pwm timings (ccp1 and ccp2) table 2-6: capture/compare/pwm requirements (ccp1 and ccp2) param no. sym characteristic min typ? max units conditions 50* tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20 ns with prescaler 20 ns 51* tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20 ns with prescaler 20 ns 52* tccp ccp1 and ccp2 input period 3t cy + 40 n ns n = prescale value (1,4 or 16) 53* tccr ccp1 and ccp2 output rise time 25 45 ns 54* tccf ccp1 and ccp2 output fall time 25 45 ns * these parameters are characterized but not tested. ? data in "typ" column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 2-2 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode)
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 17 figure 2-9: parallel slave port timing (pic16lc74b-16/ptl16) table 2-7: parallel slave port requirements (pic16lc74b-16/ptl16) parameter no. sym characteristic min typ? max units conditions 62* tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 63* twrh2dti wr - or cs - to dataCin invalid (hold time) 35 ns 64 trdl2dtv rd and cs to dataCout valid 80 ns 65* trdh2dti rd - or cs - to dataCout invalid 10 30 ns * these parameters are characterized but not tested. ? data in "typ" column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 2-2 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
pic16lc74b-16/ptl16 ds30026a-page 18 preliminary ? 1999 microchip technology inc. figure 2-10: example spi master mode timing (cke = 0) table 2-8: example spi mode requirements (master mode, cke = 0) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time 20 45 ns 76 tdof sdo data output fall time 10 25 ns 78 tscr sck output rise time (master mode) 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 100 ns ? data in typ column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 note: refer to figure 2-2 for load conditions.
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 19 figure 2-11: example spi master mode timing (cke = 1) table 2-9: example spi mode requirements (master mode, cke = 1) param. no. symbol characteristic min typ? max units conditions 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time 20 45 ns 76 tdof sdo data output fall time 10 25 ns 78 tscr sck output rise time (master mode) 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 100 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ns ? data in typ column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb note: refer to figure 2.1 for load conditions.
pic16lc74b-16/ptl16 ds30026a-page 20 preliminary ? 1999 microchip technology inc. figure 2-12: example spi slave mode timing (cke = 0) table 2-10: example spi mode requirements (slave mode timing (cke = 0) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time 20 45 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 100 ns 83 tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 ns ? data in typ column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 note: refer to figure 2-2 for load conditions.
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 21 figure 2-13: example spi slave mode timing (cke = 1) table 2-11: example spi slave mode requirements (cke = 1) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time 20 45 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 100 ns 82 tssl2dov sdo data output valid after ss edge 100 ns 83 tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 ns ? data in typ column is at 3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 note: refer to figure 2-2 for load conditions.
pic16lc74b-16/ptl16 ds30026a-page 22 preliminary ? 1999 microchip technology inc. figure 2-14: i 2 c bus start/stop bits timing table 2-12: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91* t hd : sta start condition 100 khz mode 4000 ns after this period the first clock pulse is generated hold time 400 khz mode 600 92* t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 * these parameters are characterized but not tested. note: refer to figure 2-2 for load conditions. 91 92 93 scl sda start condition stop condition 90
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 23 figure 2-15: i 2 c bus data timing table 2-13: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 m s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 m s device must operate at a minimum of 10 mhz ssp module 1.5t cy 101* t low clock low time 100 khz mode 4.7 m s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 m s device must operate at a minimum of 10 mhz ssp module 1.5t cy 102* t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91* t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the first clock pulse is generated 400 khz mode 0.6 m s 106* t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107* t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92* t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109* t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110* t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu:dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu; dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. note: refer to figure 2-2 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16lc74b-16/ptl16 ds30026a-page 24 preliminary ? 1999 microchip technology inc. figure 2-16: usart synchronous transmission (master/slave) timing table 2-14: usart synchronous transmission requirements figure 2-17: usart synchronous receive (master/slave) timing table 2-15: usart synchronous receive requirements param no. sym characteristic min typ? max units conditions 120* tckh2dtv sync xmit (master & slave) clock high to data out valid 100 ns 121* tckrf clock out rise time and fall time (master mode) 50 ns 122* tdtrf data out rise time and fall time 50 ns * these parameters are characterized but not tested. ? data in typ column is at 3v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125* tdtv2ckl sync rcv (master & slave) data setup before ck (dt setup time) 15 ns 126* tckl2dtl data hold after ck (dt hold time) 15 ns * these parameters are characterized but not tested. ? data in typ column is at 3v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 2-2 for load conditions. 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin note: refer to figure 2-2 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 25 table 2-16: a/d converter characteristics: pic16lc74b-16/ptl16-04 (commercial) param no. sym characteristic min typ? max units conditions a01 n r resolution 8 bits bit v ref = v dd a02 e abs total absolute error < 1 lsb v ref = v dd v ss v ain v ref a03 e il integral linearity error < 1 lsb v ref = v dd v ss v ain v ref a04 e dl differential linearity error < 1 lsb v ref = v dd v ss v ain v ref a05 e fs full scale error < 1 lsb v ref = v dd v ss v ain v ref a06 e off offset error < 1 lsb v ref = v dd v ss v ain v ref a10 monotonicity (note 3) guaranteed v ss v ain v ref a20 v ref reference voltage 2.5v v dd + 0.3 v a25 v ain analog input voltage v ss - 0.3 v ref + 0.3 v a30 z ain recommended impedance of analog voltage source 10.0 k w a40 i ad a/d conversion current (v dd )90 m a average current consump- tion when a/d is on. (note 1) a50 i ref v ref input current (note 2) 10 1000 10 m a m a during v ain acquisition. based on differential of v hold to v ain to charge c hold during a/d conversion cycle * these parameters are characterized but not tested. ?data in typ column is at 3v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
pic16lc74b-16/ptl16 ds30026a-page 26 preliminary ? 1999 microchip technology inc. figure 2-18: a/d conversion timing table 2-17: a/d conversion requirements param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period 2.0 m st osc based, v ref full range 3.0 6.0 9.0 m s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 11 note 2 16 11 t ad m sv dd = 3.0v, temp. = 100c, rs = 10k w 132 t acq acquisition time 5* m s the minimum time is the amplifier settling time. this may be used if the "new" input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start t osc /2 if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 135 t swc switching from convert ? sample time 1.5 t ad * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see a/d section for minimum requirements. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 134
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 27 3.0 dc and ac characteristics graphs and tables graphs and tables not available at this time.
pic16lc74b-16/ptl16 ds30026a-page 28 preliminary ? 1999 microchip technology inc. notes:
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 29 4.0 packaging information 4.1 package marking informatio n legend: mm...m microchip part number information xx...x customer specific information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week 01) c facility code of the plant at which wafer is manufactured o = outside vendor c = 5 line s = 6 line h = 8 line d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. 44-lead tqfp xxxxxxxxxx aabbcde mmmmmmmm xxxxxxxxxx example pic16lc74b-16/ptl16/pt 9911hat
pic16lc74b-16/ptl16 ds30026a-page 30 preliminary ? 1999 microchip technology inc. 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) *controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-076 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) a a1 a2 a e e1 #leads=n1 p b d1 d n 1 2 f c b l units inches millimeters* dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle f 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top a 51015 51015 mold draft angle bottom b 51015 51015 ch x 45
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 31 appendix a: revision history version date revision description a 6/99 this is a new data sheet providing the electrical specifications for the 3v, 16 mhz device. for all other information, see the pic16c63a/65b/73b/74b data sheet (ds30605).
pic16lc74b-16/ptl16 ds30026a-page 32 preliminary ? 1999 microchip technology inc. notes:
1999 microchip technology inc. preliminary ds30026a-page 33 pic16lc74b-16/ptl16 index a a/d converter characteristics .......................................... 25 timing diagram .......................................................... 26 absolute maximum ratings ................................................. 5 b brown-out reset (bor) timing diagram .......................................................... 14 c capture/compare/pwm (ccp) timing diagram .......................................................... 16 d dc characteristics ............................................................... 8 e electrical characteristics ...................................................... 5 errata ................................................................................... 2 g general description ............................................................. 3 i i 2 c (ssp module) timing diagram, data ................................................ 23 timing diagram, start/stop bits ................................. 22 p packaging .......................................................................... 29 parallel slave port (psp) timing diagram .......................................................... 17 power-on reset (por) timing diagram .......................................................... 14 product identification system ............................................ 37 r reset timing diagram .......................................................... 14 revision history ................................................................. 31 t timer0 timing diagram .......................................................... 15 timer1 timing diagram .......................................................... 15 timing diagrams and specifications .................................. 12 a/d conversion .......................................................... 26 brown-out reset (bor) ............................................. 14 capture/compare/pwm (ccp) .................................. 16 clkout and i/o ........................................................ 13 external clock ............................................................ 12 i 2 c bus data .............................................................. 23 i 2 c bus start/stop bits ............................................... 22 oscillator start-up timer (ost) ................................. 14 parallel slave port (psp) ........................................... 17 power-up timer (pwrt) ........................................... 14 reset .......................................................................... 14 timer0 and timer1 ..................................................... 15 usart synchronous receive ( master/slave) ......... 24 usart synchronoustransmission ( master/slave) .. 24 watchdog timer (wdt) ............................................. 14 u usart synchronous master mode timing diagram, synchronous receive ............ 24 timing diagram, synchronous transmission .... 24 w watchdog timer (wdt) timing diagram ......................................................... 14 www, on-line support ...................................................... 2
pic16lc74b-16/ptl16 ds30026a-page 34 preliminary 1999 microchip technology inc.
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 35 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-602-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom, mplab and fuzzy- lab are trademarks and sqtp is a service mark of micro- chip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ?device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development sys- tems, technical information and more ? listing of seminars and events 981103
pic16lc74b-16/ptl16 ds30026a-page 36 preliminary 1998 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30026a pic16lc74b-16/ptl16
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 37 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type (including lc devices). part no. -xx x /xx l16 pattern package temperature range frequency range device device pic16lc7x (1) , pic16lc7xt (2) ;v dd range 2.5v to 5.5v frequency range 04 = 4 mhz 16 = 16 mhz 20 = 20 mhz temperature range blank = 0 c to 70 c (commercial) package pt = tqfp (thin quad flatpack) pattern qtp, sqtp, code or special requirements l16 = 3v, 16 mhz examples: a) pic16lc74b-16/ptl16 = commercial temp., tqfp package, 16 mhz, low voltage v dd limits, qtp pattern #301. note 1: lc = low voltage cmos 2: t = in tape and reel - plcc, qfp, tqfp packages only.
pic16lc74b-16/ptl16 ds30026a-page 38 preliminary ? 1999 microchip technology inc. notes:
pic16lc74b-16/ptl16 ? 1999 microchip technology inc. preliminary ds30026a-page 39 notes:
? 2002 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on picmicro ? mcus. the picmicro family meets the specifications contained in the microchip data sheet. microchip believes that its family of picmicro microcontrollers is one of the most secure products of its kind on the market to day, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowl - edge, require using the picmicro microcontroller in a manner outside the operating specifications contained in the data sheet. the person doing so may be engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ? unbreakable ? . code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our product. if you have any further questions about this matter, please contact the local sales office nearest to you.
? 2002 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-6766200 fax: 86-28-6766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 hong kong microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 01/18/02 w orldwide s ales and s ervice

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